1. Field of the Invention
This invention relates generally to the electronic package. More particularly, this invention relates to a novel technique to multiple the packing density of conventional dual in-line memory module (DIMM) package and lowering the manufacture costs while improving the thermal performance of such packages by increasing the heat spreading areas on a chip-embedded support-frame. This same folded flexible connection can further be implemented on multiple chips packaged by a ball grid array (BGA) configuration as well.
2. Description of the Prior Art
The packaging industry is constantly challenged by a great demand to increase the packing density of electronic chips. In the meantime, the packing density is limited by the rate of heat removal generated from operation of electronic components densely packed in a very small space. Use of heat spreader to effectively spreading the heat through heat conductivity over the heat spreader is commonly applied. However, use of heat spreader along does not provide an effective solution to double or even multiple the packing density of the electronic chips in a packaging assembly.
In addition to above difficulties, many chip-set providers would like to have multiple chips assembled as standard package such as ball grid array (BGA) assembly in order to increase the board density with enhanced electrical performance. For example, a graphic accelerator chip is combined with memory chips and configured as side-by-side BGA package. However, there is a product yield difficulty related to a requirement that if either one of these chips fails during the test processes, the entire BGA package is useless and must be discarded. The yield of this BGA package can be improved by using a known good die (KGD) for the graphic accelerator and the memory. However, due to the price of KGD, the cost of such package would become unreasonably high. Furthermore, the side-by-side configuration even results in enhanced performance, can only achieve small improvement in packing density due to the inherent nature of such configuration that these two chips are spread out as a side-by-side chip-array on a same horizontal plane.
Additionally, for many applications, it is often desirable to assemble chips or devices manufactured with different technologies into a single standard package such as ball-grid array (BGA) in order to increase board density and enhance electrical performance. Specific examples of such packages may include a processor chip such as a digital signal processor (DSP), a microprocessor or graphic accelerator chip packaged with memory chips as a single BGA package. For portable electronic applications, it may be desirable to package flash memories with static RAM. Broader applications may include assemble silicon integrated circuits (IC) with micro electronic mechanical system (MEMS) or optical devices in a single package. Devices made with different technologies may compose different materials and mounted on different substrates such as ceramic, glass, polyimide film or printed-circuit-board (PCB). Therefore, these devices and their supporting substrates generally have different operational characteristics and often become difficult for integration particular integration of these devices into a rigid single package. Particularly, current configuration by stacking multiple dices in a single package presents great challenges to provide such an integrate package to accommodate different requirements arising from different operation characteristics.
Furthermore, when multiple chips and devices are mounted on a single supporting substrate as a multiple chip module, the requirement of using only the know-good-die (KGD) becomes a cost issue. However, this issue cannot be easily resolved because a small percentage of failed chips of each kind of different chips or devices may significantly reduce the production yield and make the production cost even more expensive. This difficulty is caused by a very realistic problem that a single failed chip among several chips of the MCM module would force one to discard the entire module. In addition to the issues of production yield, the package density cannot be increased when all the chips are placed on a single horizontal plane.
Kim et al. disclose in U.S. Pat. No. 6,225,688 a stacked microelectronic assembly with a structure that includes a flexible substrate having a plurality of attachment sites, test contacts and conductive terminals. The assembly further includes a wiring layer with leads extending to the attachment sites. The assembly assembles a plurality of microelectronic elements to the attachment sites and electrically interconnecting the microelectronic elements and the leads. The flexible substrate is folded so as to stack at least some of the microelectronic elements in substantially vertical alignment with one another to provide a stacked assembly with the conductive terminals exposed at the bottom end of the stack and the test contacts exposed at the top end of the stack. The assembly may be made using a dam and or a spacer to facilitate the folding process. Two stacked microelectronic assemblies may be stacked together by providing a first stacked assembly with a plurality of connection pads exposed at the top end and providing a second stacked assembly with a plurality of solder balls connected to the terminals at the bottom end. By connecting the solder balls to the connection pads, the first assembly and the second assembly may be stacked as a stacked assembly.
The electronic assembly as disclosed by Kim et al. in U.S. Pat. No. 6,225,688 is however still have the limitations and difficulties that the reliability of the package is adversely affected by the mismatch of the coefficient of thermal expansion (CTE) between flexible substrate and the PBC substrate board. Also the strip form of two directional folding will limit the complexity of interconnections or routings between chips to be low pin count devices such as memory products. For most memory devices, the total number of inputs and outputs are generally below fifty. But if multiple chips involved microprocessors, the total numbers of inputs and outputs will be easily over one hundred or even more. Furthermore, if one of the multiple chips fails the tests, then the entire package has to be repaired and if the failure is beyond repair the entire package has to be discarded. This creates a particular difficulty that when an expensive chip of high pin count is packaged together with peripheral chips, a package included the expensive chip may have to be discarded or great efforts are required to remove the expensive chip from the package if one of the peripheral chips fail the tests.
Therefore, a need still exits in the art to provide an improved configuration and procedure for packaging and testing the multiple chip modules to multiple the packing density without limited by difficulties of low production yield, low packing density and low heat dissipation rate. It is highly desirable to achieve a double or even multiple folds of packing density to increase the package density without being limited by the heat dissipation difficulties. There is a further need to provide edge connector configuration for standard edge insertion of a multiple-chip memory module. Also, it is desirable that for a multiple chip assembly, the difficulty of low percentage of product yield may be resolved without requiring the use of the known-good-die (KGD) for each assembly such that the production cost can be reduced.